Approximate functional matching in electronic systems

ABSTRACT

Methods and apparatuses for approximate functional matching are described including identifying functionally similar subsets of an integrated circuit design or software program, distinguishing control inputs of the subsets from data inputs, and assigning combinations of logic values to the input control signals to capture co-factors for functional matching.

This application is a divisional of U.S. patent application Ser. No. 12/204,777, filed on Sep. 4, 2008, now U.S. Pat. No. 8,453,084, issuing on May 28, 2013.

FIELD OF THE INVENTION

The invention relates generally to matching techniques for electronic systems and software programs.

BACKGROUND OF THE INVENTION

Matching techniques are often used to optimize integrated circuit designs or software programs to reduce power consumption, area and cost, or to increase performance such as operating frequency and/or data throughput. Such matching techniques have been shown to be useful in several fields including high-level synthesis of digital logic and compilers for software programs. Integrated circuits and other electronic systems include binary logic or other hardware structures to perform the functions that each circuit was designed to achieve. Likewise, compilers for software programs include data structures to perform the functions that the program was designed to achieve.

Generally, matching techniques are applied to either the structures or the functions of integrated circuit designs and software programs. Structural matching techniques seek to identify separate structures within the design of an integrated circuit or software program and to combine those structures, to the extent possible, into a single structure or subset of structures that perform the same overall function as each of the separate structures individually or the same function as all structures together. Functional matching techniques, on the other hand, seek to identify separate functions within the design of an integrated circuit or a software program and combine those functions into a single function or subset of functions that perform the same overall function as each of the separate functions individually or the same function as all structures together.

This combining of structures and/or functions may be referred to as resource sharing. FIG. 1 illustrates resource sharing among modules with identical circuitry and/or functionality according to the prior art. FIG. 1 includes two identical circuits and/or functional modules, clone A 101 and clone B 102, having the same I/O signals, IN₀ and OUT₀, respectively. Since clone A 101 and clone B 102 contain identical circuitry and/or functionality and the same I/O, clone A 101 and clone B 102 are identified as candidates for sharing. Thus, clone A 101 and clone B 102 each includes identical circuitry and/or functionality that may be shared by both clone A 101 and clone B 102. This sharing of resources among identical circuits and/or functions is achieved by replacing clone A 101 and clone B 102 with a single shared resource 103 and appropriately routing the common I/O. The structure and/or functionality of both clone A 101 and clone B 102 is maintained, but the resources required by the circuit are reduced through resource sharing.

Integrated circuit designs and/or software programs include various structures to perform various functions. These structures may include different structures that perform different functions, similar structures that perform identical functions, identical structures that perform identical functions, and different structures that perform identical functions. Likewise, integrated circuit designs and/or software programs may include identical functions implemented using identical structures, identical functions implemented using similar or different structures, different functions implemented using similar structures, and different functions implemented using different structures.

The goal of matching techniques is to identify structures and/or functionality in an integrated circuit design or software program that can be matched to enable resource sharing to the extent possible. However, previously known techniques are limited to either exact matching or matching in terms of design descriptions, leaving some matches undetected. Conventional matching techniques have been limited to either exact functional matching, or exact and approximate structural matching. For example, the 2008 publication by J. Cong and W. Jiang entitled “Pattern-based Behavior Synthesis for FPGA Resource Reduction,” Proc. ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA 2008) performs only structural matching techniques. The Cong publication finds bridging points of certain graphs to perform structural matching of integrated circuit hardware.

Several precursors of the Cong publication are also limited to structural matching including the following: L. Pozzi, K. Atasu, P. Ienne, “Exact and Approximate Algorithms for the Extension of Embedded Processor Instruction Sets,” IEEE Trans. on CAD 25(7), July 2006; X. Chen, D. L. Maskell, Y. Sun, “Fast Identification of Custom Instructions for Extensible Processors,” IEEE Trans. on CAD 26(2), February 2007; M. R. Corazao, M. Khalaf, L. Guerra, M. Potkonjak and J. M. Rabaey, “Performance Optimization Using Template Matching for Datapath-Intensive High-Level Synthesis,” IEEE Trans. on CAD 15(8), August 1996, and A. Raghunathan and N. K. Jha, “SCALP: An Iterative-Improvement Based Low-Power Data Path Synthesis System,” IEEE Trans. on CAD 16(11), November 1997.

In the category of functional matching, the recent publication by M. Ciesielski, S. Askar, D. Gomez-Prado, J. Guillot, E. Boutillon, entitled “Data-Flow Transformations using Taylor Expansion Diagrams,” Proc. ACM/IEEE Design Automation Conference (DAC) 2007, performs exact functional matching only. Likewise, the publication by P. Tummeltshammer, J. C. Hoe, M. Pueschel, entitled “Time-Multiplexed Multiple-Constant Multiplication,” IEEE TCAD 26(9), September 2007 is based on exact functional matching. The Tummeltshammer publication is applicable only to subsets of designs that perform multiplication by pre-determined constants, and only in the context of multiplication circuits. An earlier publication by P. Flores, J. Monteiro, E. Costa, entitled “An Exact Algorithm for the Maximal Sharing of Partial Terms in Multiple Constant Multiplications”, Proc. ACM/IEEE Int'l Conf. on CAD (ICCAD 2005) on sharing resources among multiplication circuits exhibits the same limitations as Ciesielski and Tummeltshammer. The publication by A. Verma and P. Ienne entitled, “Improved use of the carry-save representation for the synthesis of complex arithmetic circuits,” in Proceedings of ICCAD 2007 discloses a representation of arithmetic circuits that facilitates algorithms for exact functional matching. Similar techniques based on circuit transformations have been pursued in more recent art, but generally share the same limitations.

In the case of functional matching, it is well-known that designs that perform the same function, regardless of their internal structure, can be functionally matched to enable resource sharing. In the case of structural mapping, identical or similar structures may be matched whether or not they perform identical functions.

Another line of prior art is motivated by techniques that have been proposed for specialized physical layout of datapath circuits, exemplified by the U.S. Pat. No. 5,737,237 entitled “Method and apparatus for data path circuit layout design and memory medium for causing computer to execute datapath design,” and U.S. Pat. No. 6,560,761 entitled “Method of datapath cell placement for bitwise and non-bitwise integrated circuits.” These techniques teach receiving as input a datapath description for a datapath block and either prepare or receive function macros in each of which there is a defined expansion to a circuit comprising a plurality of schematic leaf cells. These techniques are commonly described for gate-level circuits.

In practice, datapath circuits can and often are extracted by design engineers. Since datapaths circuits (particularly adders and multipliers) may admit compact and regular layout, attempts have been made at “regularity extraction,” often focusing on array-like structures and repeated components. S. Hassoun and C. McCreary in their ICCAD 1999 paper entitled, “Regularity extraction via clan-based structural circuit decomposition,” points out that identifying repeating structural regularities in circuits allows the minimization of synthesis, optimization and layout efforts. They term these repeated structures “templates” and cover the circuit with an appropriate set of templates. U.S. Pat. No. 6,148,433 entitled, “Systematic approach for regularity extraction,” also teaches generating a set of templates for a circuit through computer automated operations on a description of the circuit. The method includes covering the circuit with instances of a subset of the templates. Such templates may include adders, multipliers, and larger configurations.

S. R. Arikati and R. Varadarajan in their ICCAD 1997 paper entitled, “A signature based approach to regularity extraction,” computes numerical signatures of circuit components and identifies similar components when different signatures match. U.S. Pat. No. 6,557,159 entitled, “Method for preserving regularity during logic synthesis,” also determines a group of elements in a circuit netlist having similar regularity signatures. In this case, regularity is determined based on a physical layout of the circuit. Further, this patent teaches determining a regularity signature for each element within the group and determining whether the regularity signatures for each element are identical.

U.S. Pat. No. 7,337,418 entitled, “Structural regularity extraction and floorplanning in datapath circuits using vectors,” distinguishes a functional regularity extraction component, a structural regularity extraction component, and a floorplanning component. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. While particularly noting regularity in datapath circuits and focusing on templates, this patent also teaches identifying control logic for the logic design and excluding the control logic from the set of vectors. A vector is a group of template instances that are identical in function and in structure. The techniques described in this patent are structural as they consider two subgraphs functionally equivalent, if and only if the following: (a) if they are isomorphic' (b) the logic functions of corresponding nodes are the same; and (c) the indices of corresponding edges are also the same. Under this criterion, the functional equivalence of (a+b)*c and (a*c+b*c), even though obvious to a person skilled in the art, cannot be established. While focusing on template covering and physical layout, the patent does not explain how one may identify control or datapath.

SUMMARY OF THE DESCRIPTION

Embodiments described herein include a method and computer-readable medium to perform a method, the method comprising locating one or more subsets of an integrated an integrated circuit or software program with similar functionality and/or subsets with functionality similar to a given template, assigning combinations of logic values to the control inputs of the subsets to capture a plurality of co-factors performed by the subsets for each of the combinations of logic values, and performing functional matching using the plurality of captured co-factors.

BRIEF DESCRIPTION OF THE DRAWINGS

A better understanding of at least certain embodiments of the invention can be obtained from the following detailed description in conjunction with the following drawings, in which:

FIG. 1 illustrates resource sharing among modules with identical circuitry and/or functionality according to the prior art.

FIG. 2A illustrates an implementation of a 4-input multiplexor circuit.

FIG. 2B illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-input multiplexor according to an exemplary embodiment of the invention.

FIG. 2C illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-input multiplexor according to an exemplary embodiment of the invention.

FIG. 2D illustrates an implementation of a 2-input binary decoder circuit.

FIG. 2E illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 2-input binary decoder circuit according to an exemplary embodiment of the invention.

FIG. 2F illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 2-input binary decoder circuit according to an exemplary embodiment of the invention

FIG. 3A illustrates an implementation of a 4-output demultiplexer circuit FIG. 3B illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-output demultiplexer circuit according to an exemplary embodiment of the invention.

FIG. 3C illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-output demultiplexer circuit according to an exemplary embodiment of the invention.

FIG. 4A illustrates an implementation of a 1-bit full adder circuit.

FIG. 4B illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 1-bit full adder circuit according to an exemplary embodiment of the invention.

FIG. 4C illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into input Cin of a 1-bit full adder circuit according to an exemplary embodiment of the invention.

FIG. 4D illustrates an implementation of a carry-ripple adder.

FIG. 5A illustrates a method for determining control inputs in an integrated circuit design or software program according to an exemplary embodiment of the invention.

FIG. 5B illustrates a method for determining control inputs in an integrated circuit design or software program according to an exemplary embodiment of the invention.

FIG. 6 illustrates a method of approximate functional matching according to an exemplary embodiment of the invention.

FIG. 7 illustrates an exemplary data processing system upon which the methods and apparatuses of the invention may be implemented.

DETAILED DESCRIPTION

Throughout the description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form to avoid obscuring the underlying principles of embodiments of the present invention.

A method and apparatus for approximate functional matching in electronic systems is described. At least certain embodiments identify approximate functional matches not found by previously existing techniques. These embodiments simultaneously remove the restrictions of exact functional matching and structural matching taught in the prior art by matching one or more subsets of an integrated circuit design or software program (hereinafter referred to collectively as “subsets”) to one or more templates, or by matching two or more subsets to each other. Some embodiments match subsets with different descriptions but very similar function, without requiring the function to be identical. This can be done by analyzing a description of an integrated circuit design or software program looking for subsets with similar function and/or subsets whose function is similar to a given template. In both cases, the structural descriptions of the subsets may be unrelated, or unrelated to the structural descriptions of the given templates. The matched subsets need not be exact (or identical to each other), but may differ in various respects.

Embodiments first consider one or more subsets of an integrated circuit design or software program with similar function and/or subsets whose function is similar to a given template. Embodiments then identify control inputs in the subsets and/or templates, or read an already prepared description identifying the control inputs. In the former case, embodiments evaluate the impact of assigning logic values to a given input. If this impact is deemed significant, the input is labeled as a control input (several criteria can be used to determine significant impact, e.g., if some other inputs are made irrelevant or if the support of some outputs changes significantly).

The identified control inputs are then used in certain embodiments to capture a plurality of co-factors (or special-case functions). By separating the overall function of a subset into a plurality (such as an ordered set or vector) of such co-factors, embodiments can leverage other functional matching techniques, including known techniques for exact functional matching. In at least certain embodiments, this process is referred to as approximate functional matching, since functional matching may be performed on matching candidates (subsets) with similar, but not exact functionality. If multiple or all co-factors match for two or more subsets or for one or more subsets and a template, then an approximate match is declared. An approximate match is also an exact match if for every control-input combination the co-factors match. In this way, embodiments can locate approximate functional matches not found by prior art solutions. This can lead to a multitude of benefits in various applications, including better utilization of available resources, smaller chip size, smaller manufacturing cost, and smaller power consumption.

I. First Criterion for Identifying Control Signals

In at least certain embodiments, control signals must be distinguished from data signals. Word-level and Boolean decision diagrams can be combined to represent datapaths and control, using hybrid decision diagrams or by adding ROBDD-like multiplexor nodes to word-level decision diagrams. Either way, data must first be distinguished from control. Control signals generally appear in the middle of a circuit after data comparisons, and can be clustered into multibit control values. In one embodiment, inputs may be evaluated using two criteria. The first criterion is to perform constant propagation on a given input to compare sets of internal signals made unobservable. That is, control signals may be identified by independently propagating binary values of 0 and 1 through inputs of an integrated circuit or software program to simplify the resulting netlist. If constant propagation of binary values of 0 and 1 substantially impacts the resulting circuit or program, the signal may be considered control. However, there is no hard and fast rule as to what criteria may be used to determine whether an input is data or control as several criteria may be used independently or in combination with each other including whether the input values activate very different regions of the design, if other inputs are made irrelevant by combinations of the input values, or if the support of some output changes substantially, to name a few. The determination of control signals may vary from implementation to implementation. What is determined to be control in one circuit or program may be determined to be data in another. These judgments may be implementation specific based on various factors including the type of circuit or program as well as individualized needs of users and/or administrators.

For example, an explicit multiplexor is a well-known circuit configuration containing control circuitry. FIG. 2A illustrates an implementation of a 4-input multiplexor circuit. 4-input multiplexor circuit 231 includes inputs In₀, In₁, In₂, In₃, En (enable), S₀, and S₁. The internal logic of 4-input multiplexor 231 is illustrated at the bottom portion of FIG. 2A including inverters 239-240, AND gates 233-236, and OR gate 237. The equation represented by 4-input multiplexor 231 is as follows:

Out=En·[(In ₀ S ₁ ′S ₀′) OR (In ₁ S ₁ ′S ₀) OR (In ₂ S ₁ S ₀′) OR (In ₃ S ₁ S ₀)]

Control inputs may be identified by determining the impact of the resulting netlist when constant propagation of the binary values of 0 and 1 is applied to the inputs. FIG. 2B illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-input multiplexor according to an exemplary embodiment of the invention. In the illustrated embodiment, when S₁ is set =0, circuit 231 reduces to the simple AND-OR circuit shown at the top portion of FIG. 2B including only inverter 240, AND gates 235-236, and OR gate 237. This can be seen by setting S₁=0 in the above equation resulting in the equation:

Out=En·[(In ₀·1·S ₀′) OR (In ₁·1·S ₀) OR (In ₂·0·S ₀′) OR (In ₃·0·S ₀)]

which simplifies to,

Out=En·[(In ₀·1·S ₀′) OR (In ₁·1·S ₀)].

With reference to the circuit elements of FIG. 2A, whenever input S₁ is set =0, the value 0 is propagated to inverter 239, and AND gates 235-236. Inverter 239 will always output a 1 when input S1 is set =0, therefore inverter 239 is removed and a value of 1 is propagated to AND gates 233 and 234. Whenever an AND function is applied to “anything” and the value 1, the “anything” is propagated to the output. Since the output of inverter 239 is equal to the value of 1, the AND gate 233 and 234 may be simplified into 3-input AND gates. The output of AND gate 233 will always be the AND of inputs In₀, En, and S₀′. Therefore, the constant propagation of the value of 0 at input S₁ results in reducing circuit 231 as illustrated in the top portion of FIG. 2B. Likewise, the constant propagation of the value of 1 at input S₁ results in reducing circuit 231 as illustrated in the lower portion of FIG. 2B.

In at least certain embodiments, the impact of the applying the above constant propagation on inputs of an integrated circuit or computer program is determined. If this impact is deemed significant enough, the input is determined to be a control input. Otherwise, the input is determined to be data. In previous computer implemented methodologies, signals were always classified as either data or control signals with no overlap. In contrast, embodiments provide a spectrum of signal classifications with some signals being classified as definitely control signals, definitely data signals, or anywhere in-between. Inputs may then be determined to be more control than data. Likewise, inputs may be determined to be more data than control. As discussed above, in some embodiments this determination may be made based on the impact of constant propagation of the binary values of 0 and 1 at inputs of an integrated circuit or software program, and subsequently judging the impact on the resulting circuit. Accordingly, embodiments envision signals that are almost determined to be data signals, but not quite. Likewise, embodiments envision signals that are almost determined to be control signal, but not quite.

In the illustrated embodiment of FIGS. 2A and 2B, it is clear that applying constant propagation to the input S₁ substantially reduces the circuit 231. However, applying constant propagation to other inputs may result in only a minor or insubstantial impact on the resulting circuit 231. FIG. 2C illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-input multiplexor according to an exemplary embodiment of the invention. In the illustrated embodiment, whenever In₀ is set =0, circuit 231 reduces slightly to the circuit illustrated at the top portion of FIG. 2C including inverters 239-240, AND gates 234-236, and OR gate 237. Likewise, the constant propagation of the value of 1 at input In₀ results in reducing circuit 231 as illustrated in the lower portion of FIG. 2B.

In this case, applying constant propagation of binary values 0 and 1 to input In₀ may be deemed (based on selected criteria discussed above) to reduce the logic of circuit 231 substantially less than applying constant propagation of binary values of 0 and 1 to input S₁. In at least certain embodiments, the impact of performing the above constant propagation on input S₁ may be deemed significant enough for S₁ to be determined to be a control signal rather than data, whereas the impact of performing constant propagation on input In₀ may be deemed too insubstantial for In₀ to be determined to be a control signal. However, as discussed above, different impacts on a particular circuit may be judged differently depending on any number of criteria discussed above including whether the input values activate very different regions of the design, if other inputs are made irrelevant by combinations of the input values, or if the support of some output changes substantially.

Another example is demonstrated in FIGS. 2D-2F. FIG. 2D illustrates an implementation of a 2-input binary decoder circuit. 2-input decoder 201 includes inputs In₀, In₁, En (enable) and outputs Out₀, Out₁, Out₂ and Out₃. The internal logic of 2-input decoder 201 is illustrated in the lower portion of FIG. 2D including inverters 219-220, and AND gates 211-214. The equations represented by 2-input decoder 201 are as follows:

Out₀ =In ₁ ′·In ₀ ′·En

Out₁ =In ₁ ′·In ₀ ·En

Out₂ =In ₁ ·In ₀ ′·En

Out₃ =In ₁ ·In ₀ ·En

In certain embodiments, control inputs may be identified by determining the impact of the resulting netlist when inputs are constant propagated with the binary values of 0 and 1. FIG. 2E illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 2-input binary decoder circuit according to an exemplary embodiment of the invention. In the illustrated embodiment, whenever In₀ is set =0, circuit 201 reduces to the simple AND circuit shown at the top portion of FIG. 2E including only inverter 220, and AND gates 211 and 213. This can be seen by setting In₀ to 0 in the above equation resulting in the following equations:

Out₀ =In ₁′·1·En

Out₁ =In ₁′·0·En

Out₂ =In ₁·1·En

Out₃ =In ₁·0·En

which simplifies to,

Out₀ =In ₁ ′·En

Out₁=0

Out₂ =In ₁ ·En

Out₃=0

Likewise, the constant propagation of the value of 1 at input In₀ results in reducing circuit 201 as illustrated in the lower portion of FIG. 2E. In the illustrated embodiment of FIGS. 2D and 2E, it is not necessarily unambiguous that applying constant propagation to the input In₀ substantially reduces the circuit 201. However, applying constant propagation to other inputs may result in a substantial impact on the resulting circuit 201. FIG. 2F illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 2-input binary decoder circuit according to an exemplary embodiment of the invention. In the illustrated embodiment, whenever En is set =1, circuit 201 reduces slightly to the circuit illustrated at the top portion of FIG. 2F including inverters 219-220 and AND gates 212 and 214. Thus, the impact of propagating the constant binary value of 1 to input En may be deemed insubstantial based on this result. In contrast, the constant propagation of the value of 1 at input En may be deemed to be substantial since it results in reducing circuit 201 as illustrated in the lower portion of FIG. 2F. In at least certain embodiments, therefore, input En may be determined to be a control signal rather than data based on the criteria discussed above since applying constant propagation of binary values 0 and 1 to input En reduces the logic of circuit 201 substantially more than applying constant propagation of values of 0 and 1 to input In₀. As a result, the impact of performing the above constant propagation on input En may be deemed significant enough for En to be labeled as a control signal rather than data, whereas the impact of performing constant propagation on input In₀ may be deemed too insubstantial for In₀ to be determined to be a control signal.

II. Second Criterion for Identifying Control Signals

Sometimes control inputs may not be determined based on the embodiments described above. In such cases, embodiments describe a second criterion which may be used to distinguish control signals form data signals. The second criterion is not mutually exclusive from the first criterion discussed above. The two criteria may either be performed independently and/or in conjunction with each other. An example of using the second criterion in conjunction with the first criterion is demonstrated in FIGS. 3A-3C. FIG. 3A illustrates an implementation of a 4-output demultiplexor circuit. 4-output demultiplexer 301 includes inputs S₀, and S₁, In, and outputs Out₀, Out₁, Out₂ and Out₃. The internal logic of 4-output demultiplexor 301 is illustrated in the lower portion of FIG. 3A including inverters 339-340 and AND gates 333-336. The equations represented by 4-output demultiplexor 201 are as follows:

Out₀ =S ₁ ′·S ₀ ′·IN

Out₁ =S ₁ ′·S ₀ ·IN

Out₂ =S ₁ ·S ₀ ′·IN

Out₃ =S ₁ ·S ₀ ·IN

In certain embodiments, control inputs may not be identified by determining the impact of the resulting netlist when inputs are constant propagated with the binary values of 0 and 1. In this case, the first criterion may not correctly identify control inputs. FIG. 3B illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-output demultiplexer circuit according to an exemplary embodiment of the invention. In the illustrated embodiment, whenever input IN is set =0, circuit 301 reduces to a simple ground (GND) circuit with all outputs tied to voltage ground (binary 0). This can be seen by setting In =0 in the above equation resulting in the following equations:

Out₀ =S ₁ ′·S ₀′·0

Out₁ =S ₁ ′·S ₀·0

Out₂ =S ₁ ·S ₀′·0

Out₃ =S ₁ ·S ₀·0

which simplifies to,

Out₀=0

Out₁=0

Out₂=0

Out₃=0

Likewise, the constant propagation of the value of 1 at input IN results in reducing circuit 301 as illustrated in the lower portion of FIG. 3B. In the illustrated embodiment of FIG. 3B, the impact of applying constant propagation of the values of 0 and 1 to input IN may be considered ambiguous. In the top portion of FIG. 3B, setting IN =0 substantially simplifies the circuit 301, whereas in the lower portion of FIG. 3B, setting IN =1 hardly changes circuit 301 at all.

FIG. 3C illustrates special-case circuits (co-factors) resulting from propagating constant binary values of 0 and 1 into an input of a 4-output demultiplexer circuit according to an exemplary embodiment of the invention. In the illustrated embodiment, whenever input S₁ is set =0, circuit 301 is reduced to the circuit shown in the top portion of FIG. 3C. Likewise, the constant propagation of the value of 1 at input S₁ results in reducing circuit 301 as illustrated in the lower portion of FIG. 3C. In the illustrated embodiment of FIG. 3C, the impact of applying constant propagation of the values of 0 and 1 to input S₁ may be considered ambiguous. This is because propagating the constant binary values of 0 and 1 to input S₁ reduces circuit 301 somewhat. In at least certain embodiments, this impact may be deemed too insubstantial to be considered a control input.

In these cases, the first criterion may not correctly identify control inputs and the second criterion may be used. The second criterion determines the number of bit-signals controllable by a given input signal. That is, the second criterion determines the amount of outputs that are sensitized by a given input. An input sensitizes a given output whenever a logic transition at the input produces a logic transition at the given output for various configurations of side-inputs. To check each downstream signal, an SAT-based Boolean-difference computation or ATPG-style justification can be used. For example, referring back to FIG. 3A, the second criterion is applied to inputs X and S₁. When the second criterion is applied to input X, the side-inputs will be S₁ and S₀. The second criterion determines how many outputs are sensitized by a transition in X for given values of S₁ and S₀. The following table summarizes the results of a logic transition in X for each combination of values of S₁ and S₀:

Outputs Assigned Assigned Sensitized by Values of S₁ Values of S₀ transition of X 0 0 Out₀ 0 1 Out₁ 1 0 Out₂ 1 1 Out₃

Table 1.1 illustrates various outputs sensitized by input X.

A transition in the logic value of X for each combination of S₁ and S₀ sensitizes at most only one (1) output as indicated by table 1.1 above. In at least certain embodiments, sensitizing only one output may not be considered significant enough to label X as a control signal. In such a case, the input X may be considered to be a data signal rather than a control signal.

When the second criterion is applied to input S₁, on the other hand, the side-inputs will be X and S₀. The second criterion determines how many outputs are sensitized by a transition in S₁ for given values of X and S0. The following table summarizes the results of a logic transition in S₁ for each combination of values of X and S₀:

Outputs Assigned Assigned Sensitized by Values of S₀ Values of X transition of S₁ 0 0 None 0 1 Out₀, Out₂ 1 0 None 1 1 Out₁, Out₃

Table 1.2 illustrates various outputs sensitized by input X.

A transition in the logic value of S₁ for each combination of X and S₀ sensitizes as many as two (2) outputs as indicated by table 1.2 above. This is half of the total outputs in circuit 301, and in at least certain embodiments, sensitizing half of the outputs in a particular circuit may be considered significant enough to label S₁ as a control signal. As discussed above, however, there is no hard-and-fast rule, and whether a signal is determined to be control or data may vary from case to case.

In this manner, the second criterion may identify control signals not identified using the first criterion alone. This is particularly useful for identifying demultiplexors (such as circuit 301) and add/subtract control lines of adders/subtractors.

Other times ambiguous findings may result using both of the above methods. FIG. 4A illustrates an implementation of a 1-bit full adder circuit. 1-bit adder 401 includes inputs A, B and Cin, and outputs Cout and S (sum). The internal logic gates of 1-bit adder 301 are shown in the bottom portion of FIG. 4A including exclusive-OR (XOR) gates 411-412, AND-gates 413-414, and OR-gate 415. The equations represented by 1-bit adder 401 are as follows:

S=(A XOR B) XOR Cin

Cout=(A·B) OR (Cin·(A XOR B))

In these embodiments, however, control inputs may not be properly identified by determining the impact of the resulting netlist when inputs are constant propagated with the binary values of 0 and 1. Additionally, control inputs may not be properly identified by determining how many outputs are sensitized by a given input. FIG. 4B illustrates special-case circuits (co-factors) resulting from applying constant propagation of binary values 0 and 1 to an input of a 1-bit full adder circuit according to an exemplary embodiment of the invention. In the illustrated embodiment, when input A is set to 0, circuit 401 reduces to the half-adder circuit shown in the top portion of FIG. 4B including only XOR gate 412 and AND gate 413. The logic functions of XOR gate 411, AND gate 414, and OR gate 415 have been resolved by propagating the value 0 of input A. This can be seen by setting A=0 in the above equation resulting in the following equations:

S=(0 XOR B) XOR Cin

Cout=(0·B) OR (Cin·(0 XOR B))

which simplifies to,

S=B XOR Cin

Cout=Cin·B

This can also be seen by referring back to FIG. 4A. Whenever input A is set =0, the inputs of XOR 411 are 0 and B. Whenever the value of a first input to an XOR gate is =0, the output value will be equal to the value of the other input(s) to the XOR gate, in this case B. So, input B propagates through to the input of XOR 412. XOR 411 is removed. Likewise, when input A is set =0, the inputs of AND 414 are 0 and B. Thus, 0 propagates through to the input of OR gate 415, and AND gate 414 is removed. Now the inputs to OR gate 415 are the output of AND 413 and 0. Whenever a first input to a 2-input OR gate is a 0, then the output will be equal to the value of the other input(s). In this case the output of AND 413 is the other input of OR gate 415 and, therefore, the output of AND 413 propagates through to Cout. OR gate 415 is removed. The resulting circuit is shown in the top portion of FIG. 4B. Similarly, when input A is set =1, circuit 401 reduces to the circuit shown in the bottom portion of FIG. 4B including only XOR gate 412, AND gate 413, inverter 417 and OR gate 415. It is noted that XOR 211 reduces to inverter 417. The logic functions of XOR gate 411 and AND gate 414 have been resolved by propagating the value 1 into input A.

Similarly, FIG. 4C illustrates special-case circuits (co-factors) resulting from applying constant propagation of binary values 0 and 1 to input Cin of a 1-bit full adder circuit according to an exemplary embodiment of the invention. In the illustrated embodiment, when input Cin is set =0, circuit 401 reduces to the half-adder circuit shown in the top portion of FIG. 4C including only XOR gate 411 and AND gate 414. The logic functions of XOR gate 412, AND gate 413, and OR gate 415 have been resolved by propagating the value 0 of input Cin. When input Cin is set =1, circuit 401 reduces to the circuit shown in the bottom portion of FIG. 4B including only XOR gate 412, AND gate 413, inverter 417 and OR gate 415. It is noted that XOR 411 reduces to inverter 417. The logic functions of XOR gate 411 and AND gate 414 have been resolved by propagating the value 1 of input A.

In the case of 1-bit full adder circuit 401, the impact of propagating constant values of 0 and 1 into inputs A and Cin may be considered to have yielded ambiguous results. Performing constant propagation on inputs A and Cin both yielded reduced circuits with the same number of gates in both cases. This being the case, a decision as to whether each input A and Cin should be considered control or data may be tough to determine. In at least certain embodiments, this may be resolved by evaluating the inputs A and Cin using the second criterion of determining how many outputs are sensitized by a given input may be performed. However, the second criterion also may be considered to yield ambiguous results. For example, referring again to FIG. 4A, whenever input A of 1-bit full adder 401 is in a logic transition for various combinations of B and Cin, outputs S and Cout are both sensitized. Likewise, whenever input Cin is in a logic transition for various combinations of A and B, outputs S and Cout are also both sensitized.

Thus, under both the first and second criterion, the results may be considered ambiguous depending on the particular implementation of the 1-bit full adder 401. In such a case, it may be difficult to determine if inputs A and Cin are control signals or data. However, both A and Cin may sensitize fewer or more outputs in a chain of 1-bit full adder circuits. Typically, 1-bit adders are configured in combination with other 1-bit adders in order to perform multi-bit additions and/or subtractions. FIG. 4D illustrates an implementation of a carry-ripple adder. Adder modules can be implemented in several ways, which differ in structure, cost and speed (delay). A “carry-ripple” adder module is a multilevel network formed by the connection of 1-bit adders, called “full-adders”, as illustrated in FIG. 4D. The full-adder modules perform addition of a pair of input bits (such as inputs A and B) and a carry input (such as input Cin), producing a sum bit (S) and a carry output (Cout). That is, the inputs to full-adder i are bits A_(i) and B_(i) from the input vector, and a carry input, Cin_(i) coming from full-adder i−1. As output, full-adder i produces the sum bit S_(i) and the carry-out bit Cout_(i+1) (which is connected as carry input to full-adder i+1).

In the illustrated embodiment, it is clear that the carry-in input Cin sensitizes substantially more outputs along the carry chain than the inputs A or B to any one of the full-adders. Thus, although looking at the 1-bit adder configuration standing alone, it may be ambiguous whether inputs A, B and Cin represent data or control. However, when considering a multilevel implementation, such as the carry-ripple adder of FIG. 4D formed by the chain of 1-bit full adders 401, it may become clear that Cin is more closely akin to a control input than a data input based on the total number of outputs sensitized by the carry chain. It also may become clear that inputs A and B are more closely akin to data inputs rather than control based on the number of outputs sensitized by the inputs A and B. Accordingly, in at least certain embodiments, input Cin may be identified as a control signal by viewing the input in light of the entire multilevel implementation of the 1-bit full-adder circuit using the second criterion. Likewise, inputs A and B may be identified as data signals by viewing the inputs in light of the entire multilevel implementation of the 1-bit full-adder circuit using the second criterion.

A method for determining control inputs in an integrated circuit design or software program according to an exemplary embodiment of the invention is illustrated in FIG. 5A. The method begins by considering various candidates for matching in an integrated circuit design or software program (operation 501). This can be done in at least certain embodiments by searching for and locating subsets with similar function and/or subsets whose function is similar to a given template. In both cases, structural descriptions of the subsets may be unrelated, or unrelated to the structural descriptions of the given templates. Constant binary values of 0 and 1 are then propagated into the inputs of the identified candidates (operation 505) and the impact of the constant propagation is determined and the input is ranked with respect to other inputs (operation 507). In the illustrated embodiment, control flows to decision block 509 where it is determined whether the impact of the constant propagation is substantial enough to label the input as a control signal. As discussed previously, whether the impact of constant propagation is substantial may be relative to the particular case as implementations vary widely. If the impact of the constant propagation is considered substantial, the input is determined to be control (operation 511) and control flows to FIG. 6. If the impact of the constant propagation is not considered substantial, the potential arises that the input could be classified as data (operation 513) and control flows to FIG. 5B where the second criterion is applied to the input.

FIG. 5B illustrates a method for determining control inputs in an integrated circuit design or software program according to an exemplary embodiment of the invention. In certain cases, control signals may not properly be identified using the first criterion (method in FIG. 5A), and so, the second criterion may be applied. The number of outputs sensitized by a logic transition of an input in question is first determined (operation 515) and ranked (operation 517). For each combination of side-inputs, the number of outputs sensitized (i.e., potentially making a logic transition) for each combination of side-inputs is determined. If this number is considered substantial (operation 519), the input may determined to be a control input (operation 521). If this number of sensitized outputs is determined to be insubstantial, then the input may be determined to be data (operation 523). This completes the method of FIGS. 5A-5B.

III. Approximate Functional Matching

With control inputs known and ranked, various combinations of the control inputs may be applied to the identified control signals to reduce the integrated circuit or software program to a subset that can be matched to templates and/or other subsets using known matching techniques. Using the control rankings, a small subset of control signals is found and all possible combinations of the subset of control signals is considered. A series of co-factors may then be captured by toggling combinations of values of the control inputs. Specifically, for a known control input set, the function performed by the circuit or software program may be captured by assigning various combinations of logic values to the control inputs. Each combination of control inputs assigned may reduce the circuit or software program. For each combination, the reduced circuit or software program is captured as a co-factor (special-case function), which may be represented as a plurality (ordered set or vector) of co-factors, each corresponding to a particular combination of values assigned to the control inputs.

Thus, in embodiments, control inputs are first identified using the first criterion and/or the second criterion discussed above, then the co-factors of a circuit or program are captured by assigning various combinations of these control inputs. The co-factors may then be matched using known functional matching techniques. For example, assuming that the signals S₁ and S₀ are identified as control signals in FIG. 2A, then assigning various logic values to these control inputs yields a number of co-factors which can then be matched using existing techniques. The equation given above describing circuit 231 is as follows:

Out=En·[(In ₀ S ₁ ′S ₀′) or (In ₁ S ₁ ′S ₀) or (In ₂ S ₁ S ₀′) or (In ₃ S ₁ S ₀)],

When combinations of control inputs are assigned to the values of S₁ and S₀, the following co-factors result:

Assigned Assigned Captured Values of S₁ Values of S₀ co-factors 0 0 Out = En · In₀ 0 1 Out = En · In₁ 1 0 Out = En · In₂ 1 1 Out = En · In₃

Each of the co-factors in the above case reduces circuit 231 of FIG. 2A down to a single AND gate structure each with the common input driven by input En. These simple enable-driven AND gate structures then become candidates for matching, and may subsequently be matched to one or more templates, or one or more other candidates for matching so identified in an integrated circuit design or software program.

This matching may be performed using any known functional matching techniques. Some embodiments match subsets with different descriptions but very similar function without requiring the function to be identical. Thus, approximate functional matching may be performed on one or more identified matching candidates according to the principles outlined in this description. These identified matching candidates may then be evaluated and possibly ranked based on overall resource savings they could provide to the circuit or program.

FIG. 6 illustrates a method of performing approximated functional matching according to an exemplary embodiment of the invention. As discussed above, combinations of values of the identified control inputs are assigned (operation 601) and co-factors are captured for each of the assigned combinations (operation 603). Then functional matches are found among the co-factors using known matching techniques (operation 605). These techniques may be used with integrated circuits and software programs. For example, a subset of the software program can be a function (using C++ syntax) such as:

int max (int a, int b) { return (a>b ? a : b); } Or double max (double a, double b) {  return (a>b ? a : b); } For these simple programs, a “control input” would be the type used (or a collection of types). A super-function that explicitly exposes the type as a parameter would be as follows:

template<class T> T max (T a, T b) { return (a>b ? a : b); } Not only functions, but also fragments of functions can be eligible subsets. For example:

for (int i=0; i++; i<N) { c[i]=a[i]+gamma*b[i]; } would match for (int j=0; j++; j<M) { z[i] =x[i] +delta*y[i]; }

Once the matching candidates are identified, known matching techniques may be applied. One technique is to conglomerate adjacent matches into clusters to reduce multiplexing overhead. For example, for the subsets represented by the equations (A+B)*C and (X+Y)*Z, the adders and the multipliers would be identified as matching candidates (even though the inputs are different). If each of the subsets is multiplexed onto itself, then two (2) multiplexors and two (2) demultiplexors would be required. However, if the matches are conglomerated into an adder-multiplier supermodule, then only one (1) multiplexor is required.

Another matching technique is to match functional equivalents with different internal structure. For example, the subsets represented by the equations (A+B*C) and (A*C+B*C) are functionally equivalent and may be matched as so even though they have different structure. Similarly, structural equivalence can often be relaxed by several gates which can then be multiplexed. For example, an unmatched inverter can be turned into an XOR gate controlled by an identified control input such as a thread_id.

Moreover, different modules can be generalized into a configurable supermodule of approximately the same size, e.g., addition, subtraction and less-than comparisons can be performed by one supermodule with two (2) select lines. Instead of using a separate adder and subtractor in this example, a standard adder-subtractor may be used with a configuration bit. Consider building an adder-subtractor from an adder and a subtractor. Once a 4-bit adder-subtractor is built by approximate functional matching, it is known that its add-or-subtract configuration bit is control, and everything else is data. So, when approximate functional matching is performed bit-by-bit, the two cases of “add” and “subtract” are considered with two new data bits which can be used for co-factoring. This gives three control signals and eight cofactors. Since all cofactors must match, one additional bit of the result can be computed by finding only several gates.

If many pairs of co-factors match, they can be multiplexed to build up a supermodule that can act as a constituent component to be matched with other supermodules (depending on select bits). The supermodule may then be optimized. For example, the expressions (sel ? A+B:A-B) and (sel ? A-B:A+B) can be viewed as multiplexors selecting between values of A+B and A-B computed by an adder and a subtractor. But, they do not match exactly because they differ by an inverter on the select bit. This can be remedied using a supermodule with an XOR gate replacing the inverter controlled by thread_id (0 or 1). For thread_id 0, the circuit can be modeled by a wire, and for thread_id 1, the circuit is modeled as an inverter. This can be generalized by considering the multiplexer functional modules (x ? a:b) and (x ? b:a) as approximate matches, and their supermodule f(a, b, x, sel) can be simplified to (x XOR sel ? a:b).

A second method can be illustrated by the equivalence (sel ? a+b: a)˜(a+b & sel). This function is a ternary operator meaning, if (sel) then return a+b, else return a. This can be approximated by the expression (a+b & sel) as follows:

if sel==0, then b & sel=0, and a+b & sel=a

Generally, for small enough co-factors, say C0 and C1, approximate functional matching is performed by synthesizing the function f(x, sel)=C_(sel)(x) for every sel=0, 1. Consider two cases for sel==0 and sel==1 as follows:

f(x,0)=C0(x) and f(x,1)=C1(x).

So, f(x, sel) functionally multiplexes C0 and C1 onto the same function. In other words, f(x, sel)=(sel ? C1(x): C1(x)), which is the expression above.

To find supermodules for multiple-output circuits or software, especially arithmetics, the outputs may be ordered by the size of their support (inputs). Then the inputs may be ordered based on how many (and which) outputs they control. At least certain embodiments may then perform approximate functional matching on a few (k=4) least significant bits (LSBs). The LSBs of each of the matching candidates may be viewed as control signals and the approximate functional matching is performed as before by toggling the combinations of control inputs yielding various co-factors which may then be matched. If an acceptable supermodule is found, it may be extended in the above fashion by taking one or more LSBs of the supermodule and once again viewing these bits as control. This iteration may be performed until all inputs have been considered. However, this is given by way of illustration and not limitation as any number of inputs may be considered within the scope of this description. At each iteration, control signals are both select bit(s) of the supermodule, and the next bit(s) in the ordering. New logic (often 1-3 gates) can be found by exhaustive search or by transduction.

A particular extension of this method allows the processing of a large number of subsets and/or templates without considering all pairs. This is accomplished by using a hash function of the co-factors so as to characterize each subset by a vector of numbers. One way to perform hashing of the co-factors is to serialize their representations. Co-factors may be converted into character strings or bit-strings, and then the strings may be hashed using standard techniques. In at least certain embodiments, the vectors can then be subjected to another hash function referred to as a “locality-sensitive hash function” to arrive at a single number such that similar vectors produce similar numbers. Basically, we hash certain hash values of the co-factors, using different hash functions. Then, subsets and templates that would form approximate matches are likely to produce the same final numbers (i.e., hash into the same bucket so to speak), which allows matching co-factors to be identified efficiently without having to consider all pairs.

For example, if there are 16 co-factors and 32 co-factors, then considering all pairs would require 16*32 operations. Instead, the hash functions of the 16 and 32 co-factors may be computed and the resulting 48 values sorted into sets. This puts equal values next to each other, so that only co-factors with equal hash values are considered. If there are no equal hash values, then there will be no matches in this embodiment.

In some embodiments, a functional matching criterion can be evaluated by connecting two subsets via multiplexors and then performing known optimizations, i.e. resource sharing, factoring, constant propagation, merging equivalent selector/multiplexor inputs. The result can then be evaluated on a number of criteria such as area, timing, power relative to the same criteria for the original subsets to form a functional matching criterion.

Further, the multiplexed subsets can be converted to various functional forms for Boolean or arithmetic functions, followed by comparing characteristics of the forms such as number of nodes in graph based functional forms.

Pairs of co-factors can also be compared by connecting them via select logic and applying optimizations. The result can then be compared to the original co-factors on a variety of criteria. Again, this comparison can be based on converting the result to a functional form and measuring properties of the functional form relative to the properties of the functional forms of the co-factors.

In some embodiments, supermodules are constructed by connecting subsets via select logic and then performing optimizations to reduce the targeted criteria. If the resulting supermodule is similar in cost to the original subsets then it can potentially replace the original subsets at a savings.

Another extension of the invention is to use parametric matches and closely-related operations when capturing co-factors, such as matching an 8-bit multiplier to a 10-bit multiplier (because the latter can also implement the former) or matching an 8-bit adder to a 10-bit subtractor (for the same reason). In such cases, the more general component is considered.

In this manner, a method and apparatus for approximate functional matching in electronic systems is described. At least certain embodiments identify approximate functional matches not found by previously existing techniques. These embodiments simultaneously remove the restrictions of exact functional matching and structural matching taught in the prior art by matching one or more subsets of an integrated circuit design or software program (hereinafter referred to collectively as “subsets”) to one or more templates, or by matching two or more subsets to each other. Some embodiments match subsets with different descriptions but very similar function, without requiring the function to be identical. By separating the overall function of a subset into a plurality (such as an ordered set or vector) of such co-factors, embodiments can leverage other functional matching techniques, including known techniques for exact functional matching. In at least certain embodiments, this process is referred to as approximate functional matching, since functional matching may be performed on matching candidates (subsets) with similar, but not exact functionality. If multiple or all co-factors match for two or more subsets or for one or more subsets and a template, then an approximate match is declared. This can lead to a multitude of benefits in various applications, including better utilization of available resources, smaller chip size, smaller manufacturing cost, and smaller power consumption.

In at least certain embodiments, the foregoing methods and apparatuses described herein may be used in conjunction with any data processing system.

FIG. 7 shows one example of a typical data processing system, such as data processing system 700, which may be used with the present invention. Note that while FIG. 7 illustrates various components of a data processing system, it is not intended to represent any particular architecture or manner of interconnecting the components as such details are not germane to the present invention. It will also be appreciated that network computers and other data processing systems which have fewer components or perhaps more components may also be used. The data processing system of FIG. 7 may, for example, be a workstation, or a personal computer (PC) running a Windows operating system, or an Apple Macintosh computer.

As shown in FIG. 7, the data processing system 701 includes a system bus 702 which is coupled to a microprocessor 703, a ROM 707, a volatile RAM 705, and a non-volatile memory 706. The microprocessor 703, which may be a processor designed to execute any instruction set, is coupled to cache memory 704 as shown in the example of FIG. 7. The system bus 702 interconnects these various components together and also interconnects components 703, 707, 705, and 706 to a display controller and display device 708, and to peripheral devices such as input/output (I/O) devices 710, such as keyboards, modems, network interfaces, printers, scanners, video cameras and other devices which are well known in the art. Typically, the I/O devices 710 are coupled to the system bus 702 through input/output controllers 709. The volatile RAM 705 is typically implemented as dynamic RAM (DRAM) which requires power continually in order to refresh or maintain the data in the memory. The non-volatile memory 706 is typically a magnetic hard drive or a magnetic optical drive or an optical drive or a DVD RAM or other type of memory systems which maintain data even after power is removed from the system. Typically, the non-volatile memory 706 will also be a random access memory although this is not required. While FIG. 7 shows that the non-volatile memory 706 is a local device coupled directly to the rest of the components in the data processing system, it will be appreciated that the present invention may utilize a non-volatile memory which is remote from the system, such as a network storage device which is coupled to the data processing system through a network interface such as a modem or Ethernet interface (not shown). The system bus 702 may include one or more buses connected to each other through various bridges, controllers and/or adapters (not shown) as is well known in the art. In one embodiment the I/O controller 709 includes a USB (Universal Serial Bus) adapter for controlling USB peripherals, and/or an IEEE-1394 bus adapter for controlling IEEE-1394 peripherals.

It will be apparent from this description that aspects of the present invention may be embodied, at least in part, in software, hardware, firmware, or in combination thereof. That is, the techniques may be carried out in a computer system or other data processing system in response to its processor, such as a microprocessor, executing sequences of instructions contained in a memory, such as ROM 707, volatile RAM 705, non-volatile memory 706, cache 704 or a remote storage device (not shown). In various embodiments, hardwired circuitry may be used in combination with software instructions to implement the present invention. Thus, the techniques are not limited to any specific combination of hardware circuitry and software or to any particular source for the instructions executed by the data processing system 700. In addition, throughout this description, various functions and operations are described as being performed by or caused by software code to simplify description. However, those skilled in the art will recognize that what is meant by such expressions is that the functions result from execution of code by a processor, such as the microprocessor 703.

A machine readable medium can be used to store software and data which when executed by the data processing system 700 causes the system to perform various methods of the present invention. This executable software and data may be stored in various places including for example ROM 707, volatile RAM 705, non-volatile memory 706, and/or cache 704 as shown in FIG. 7. Portions of this software and/or data may be stored in any one of these storage devices.

The invention also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored or transmitted in a machine-readable medium. A machine readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form accessible by a machine (e.g., a computer, network device, personal digital assistant, manufacturing tool, any device with a set of one or more processors, etc.). For example, a machine readable medium includes recordable/non-recordable media such as, but not limited to, a machine-readable storage medium (e.g., any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions), or a machine-readable transmission medium such as, but not limited to, any type of electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).

Additionally, it will be understood that the various embodiments described herein may be implemented with data processing systems which have more or fewer components than system 1600; for example, such data processing systems may be a cellular telephone or a personal digital assistant (PDA) or an entertainment system or a media player (e.g., an iPod) or a consumer electronic device, etc., each of which can be used to implement one or more of the embodiments of the invention.

Throughout the foregoing specification, references to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. When a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to bring about such a feature, structure, or characteristic in connection with other embodiments whether or not explicitly described. Various changes may be made in the structure and embodiments shown herein without departing from the principles of the invention. Further, features of the embodiments shown in various figures may be employed in combination with embodiments shown in other figures.

In the description as set forth above and claims, the terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms are not intended to be synonymous with each other. Rather, in particular embodiments, “connected” is used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

Some portions of the detailed description as set forth above are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the discussion as set forth above, it is appreciated that throughout the description, discussions utilizing terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

The invention also relates to apparatus for performing the operations herein. This apparatus may be specially constructed for the required purposes, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored or transmitted in a machine-readable medium, such as, but is not limited to, a machine-readable storage medium (e.g., any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions), or a machine-readable transmission medium such as, but not limited to, any type of electrical, optical, acoustical or other form of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).

The algorithms and displays presented herein are not inherently related to any particular computer system or other apparatus. Various general purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized apparatuses to perform the method operations. The structure for a variety of these systems appears from the description above. In addition, the invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.

Embodiments of the invention may include various operations as set forth above or fewer operations or more operations or operations in an order which is different from the order described herein. The operations may be embodied in machine-executable instructions which cause a general-purpose or special-purpose processor to perform certain operations. Alternatively, these operations may be performed by specific hardware components that contain hardwired logic for performing the operations, or by any combination of programmed computer components and custom hardware components.

Throughout the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the invention. It will be apparent, however, to one skilled in the art that the invention may be practiced without some of these specific details. Accordingly, the scope and spirit of the invention should be judged in terms of the claims which follow as well as the legal equivalents thereof. 

1. A method to distinguish control inputs from data, the method comprising: determining a first number of outputs controllable by the input; and determining if the first number of outputs controllable by the input is significant enough for the input to be judged as control.
 2. The method of claim 1, wherein determining the first number of outputs controllable by the input comprises: assigning combinations of logic values to one or more side inputs of a subset of a description of an integrated circuit; and determining a second number of outputs sensitized by a logic transition of the input for a combination of values of the one or more side inputs.
 3. A computer-readable storage medium that provides instruction, which when executed by a computer performs a method to distinguish control inputs from data, the method comprising: determining a first number of outputs controllable by the input; and determining if the first number of outputs controllable by the input is significant enough for the input to be judged as control.
 4. The computer-readable storage medium of claim 3, wherein determining the number of outputs controllable by the input comprises: assigning combinations of logic values to one or more side inputs of a subset of a description of an integrated circuit; and determining a second number of outputs sensitized by a logic transition of the input for each combination of values of the one or more side inputs.
 5. The method of claim 1, wherein the input controls an output when a logic transition at the input produces a logic transition at the output for a combination of side inputs.
 6. The method of claim 1, further comprising determining the input as a control input, if the first number of outputs controllable by the input is more than a predetermined number.
 7. The method of claim 1, further comprising identifying the input as a data input, when the first number of outputs controllable by the input is less than a predetermined number.
 8. The method of claim 1, further comprising propagating logic values into the input; and determining special-case circuits resulting from propagating the logic values.
 9. The method of claim 8, further comprising determining whether the special-case circuits are smaller than an original circuit.
 10. The method of claim 1, wherein the input is part of a demultiplexor, an adder, a subtractor, or a combination thereof.
 11. The method of claim 1, further comprising ranking the control inputs.
 12. The computer-readable storage medium of claim 3, wherein the input controls an output when a logic transition at the input produces a logic transition at the output for a combination of side inputs.
 13. The computer-readable storage medium of claim 3, wherein the method further comprises determining the input as a control input, if the first number of outputs controllable by the input is more than a predetermined number.
 14. The computer-readable storage medium of claim 3, wherein the method further comprises determining the input as a data input, if the first number of outputs controllable by the input is less than a predetermined number.
 15. The computer-readable storage medium of claim 3, wherein the method further comprises propagating logic values into the input; and determining special-case circuits resulting from propagating the logic values.
 16. The computer-readable storage medium of claim 3, wherein the input is part of a demultiplexor, an adder, a subtractor, or a combination thereof.
 17. The method of claim 1, further comprising ranking the input.
 18. A data processing system comprising a memory; and a processor coupled to the memory, wherein the processor is configured to determine a first number of outputs controllable by the input, and to determine whether the first number of outputs controllable by the input is significant enough for the input to be identified as a control input.
 19. The data processing system of claim 18, wherein the processor is further configured to assign combinations of logic values to one or more side inputs of a subset; and to determine a second number of outputs sensitized by a logic transition of the input for each combination of values of the one or more side inputs.
 20. The data processing system of claim 18, wherein the input controls an output when a logic transition at the input produces a logic transition at the output for a combination of side inputs.
 21. The data processing system of claim 18, wherein the processor is further configured to determine the input as a control input, if the first number of outputs controllable by the input is more than a predetermined number.
 22. The data processing system of claim 18, wherein the processor is further configured to determining the input as a data input, if the first number of outputs controllable by the input is less than a predetermined number.
 23. The data processing system of claim 18, wherein the processor is further configured to propagate logic values into the input; and to determine special-case circuits resulting from propagating the logic values.
 24. The data processing system of claim 23, wherein the processor is further configured to determine whether the special-case circuits are smaller than an original circuit.
 25. The data processing system of claim 18, wherein the input is part of a demultiplexor, an adder, a subtractor, or a combination thereof.
 26. The data processing system of claim 18, wherein the processor is further configured to rank the input. 